ID-Xplore reached 180x faster design exploration on a real industrial 75-transistor class AB Amplifier used in RF applications. The benchmarking was performed on standard laptop with one 4-core intel processor.
Fast Exploration for Analog Design
Reaching technology limits with innovative circuit topologies is the work of the Analog Designer.
Enabling fast technology-independent analog design is the work of ID-Xplore from Intento Design.
A typical design flow requires going through "manual" sizing and biasing with lots of time consuming iterations. This empiric approach results in days of work before getting a correctly sized schematic. Only after accessing the technology PDK through ADE XL simulation can the design trade-offs be fully assessed. As semiconductor technologies have advanced, EDA innovation for DC bias and sizing has not kept pace.
Today, Intento Design ID-Xplore tool uses graph-based disruptive innovation to provide rapid, specification driven DC bias and transistor sizing. Using Cadence Virtuoso Schematic Composer Constraint Editor, design constraints plus circuit topology are used to generate a graph for fast design space exploration in any technology. ID-Xplore provides design curves showing the performance capabilities and design trade-offs within the technology and the design constraints.
The patented graph approach incorporates full technology complexity using industry standard simulators at transistor level. Specification and technology constraints drive the design exploration, ensuring a correct-by-construction DC bias operating point.
Analog Designers are empowered with fast exploration capabilities in their targeted design space to get a correct and highly performant sized schematic in minutes.
- Quickly analyze a range of DC biasing for large, complex circuits
- Understand and prioritize complex design trade-offs
- Easily explore circuit change or new topologies to meet specifications
- Easy to use design-curve interaction and back-annotation
- Re-use existing schematics to rapidly meet new specifications
- Easily migrate analog IP to another process technology
- Flexible-use, allowing for unique styles of analog design
- Schematic-centric design flow fully integrated in industry-standard design tools
- Provides rapid DC bias and W/L using transistor-level simulation
- Get solutions in minutes in the targeted design space (or show quickly no solution possible)
- Displays extensive design-space exploration results
- Allow local search refinement based on Designer directions
- Substantially increased accuracy in DC bias, including transient performance needs of highly non-linear circuits
- Back-annotates selected transistor sizing to schematic
- Operates into Cadence Analog tools as plugin
- Supports all fabrication facilities and processes
Our Professional Services team supports integration of ID-Xplore into industry-standard design flows.
We provide also Consulting Services to allow quick technology exploration and migration of Analaog Mixed Signal circuits whether this is targeting a PDK evolution or a new process node, from the same or a different foundry.
Accelerate IP Sizing, Biasing and Migration with ID-Xplore
Intento technology reduces the number of simulator calls by a factor comprised between 5 and 40.
Intento technology reduces the number of simulator calls for hierarchical designs by a factor comprised between 5 and 100.