Wanted: Analog IP Design Methodologies to Catch up with Digital Time-to-market
Chair/Organizer: Paul Stravers – Synopsys, Inc., Eindhoven, The Netherlands
Digital design scaling yields 30-40% more transistors with every technology node. But what about the scaling of analog functions? It is common to integrate analog IP designed for node N-2 in a SoC targeting node N, resulting in suboptimal analog functionality. It appears that analog designers have failed to catch up with the aggressive times-to-market required in today’s world. Possible solutions could be based on fast redesign or migration, as well as on innovative approaches to analog IP design. Whichever solution we choose, meeting the specification and the required quality criteria is mandatory! In this session we invite a silicon vendor facing these challenges, describing real-world cases and sharing their expectations for faster IP development. In addition, we will have analog IP vendors talking about emerging solutions based on either faster migration or new design methodologies.
– 49.1 How to Resize Imager IP to Improve Productivity Speaker/Author: Stephane Vivien – STMicroelectronics, Lyon, France
– 49.2 Automated Analog Design from Architecture to Implementation Speaker/Author: Saeid Ghafouri – Movellus, San Jose, CA
– 49.3 ID-Xplore: A Cognitive Software for Designing First-Time Right Analog IPSpeaker/Author: Ramy Iskander – Intento Design, Paris, France
