Intento Design at DAC 2017

Intento Design to talk and exhibit at DAC, Austin -TX, June 19-21 2017

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Come visit us at booth 1920

From June 19 to June 21 2017

Big screen for big demo on the way to accelerate design and migration phase of AMS circuits leveraging the power of graph techniques: deterministic, correct-by-construction and 100% accurate! Or how to empower Analog Designers with fast exploration capabilities in their targeted design space to get a highly performant sized schematic in minutes. 

Ramy Iskander, CEO, to talk at Si2 OpenAccess Innovation Showcase

Tuesday, June 20, 11:30 am - 1:00 pm, room 7

Intento presents Si2 OpenAccess-based constraint-driven design and migration methodology. It is based on graph theory, offering huge acceleration of both tasks at the functional level. A design graph is automatically created from OpenAccess constraint/schematic views. Each graph is deterministic, correct-by-construction and technology-independent. The key idea is to replace simultaneous resolution of linearized nodal equations inside SPICE-like simulators, by structured resolution of nonlinear DC transistor equations. Consequently, the high-order Jacobian matrices shrinks to only one element per transistor and matrix inversion is eliminated.

Ramy Iskander, CEO, to talk at Minalogic Showcase

Tuesday, June 20, from 4-6 p.m., room 8C, 2nd FLOOR MEZZANINE

This talk presents use cases to illustrate an incremental design approach to size and bias quickly analog IP. The captured designer intentions are fully constraint-driven and completely technology-independent. Fully integrated, the solution is providing acceleration as a plugin within standard analog design environment, replacing hand sizing iterations and hundreds of simulation cycles. Analog designers are empowered with new and fast exploration capabilities in a valid design space, while re-use and migration tasks are then allowed with just a couple of clicks.

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