By letting the designer explore their design intentions, see the data, and make informed decisions. Fast.
Achieving time-to-market at advanced technology nodes – the semiconductor industry perpetual challenge. Product development delay causes inventory interruption, damaged OEM client relationship, and possible market-share loss.
Industry data analysis identifies key areas for improvement – such as better design specification management, increased multi-site team communication, and more robust design capabilities for process variation (PVT).
A medium-sized multi-national semiconductor client seeking to significantly decrease product development time.
The design manager analysed actual completion times for analog design operations both at the block and system levels. Results varied significantly by the years of design experience and site location.
From industry data, the client knew key differentiators impacting corporate success included front-end design specification capabilities and team communication.
“…we encouraged analog designers to place their work inside a consistent tool flow rather than using custom scripts. This increased our ability to communicate consistently over multiple sites”, observed the design manager. “we noticed that up to 45% of our actual design time was lost to ‘design by simulation’ activities. Using this action to gain insight for design trade-offs proved to be too slow due to sequential resizing and simulation actions.”
Delayed product development at advanced nodes inevitably results in unplanned inventory shortages and leads to positioning and market-share losses.
– PVT is addressed too late in the design cycle
– Iterative design exploration is too slow
Intento Design Solution
– ID-Xplore specification-driven design exploration
– Pre-centering for “fast pass” PVT analysis
– Design space partitioning
– Graphic design space display in N-Viewer
– Multicore processing
– Up to 65% design cycle time savings
– Ability to address PVT earlier in the design cycle
The design manager noted that after sizing was complete and verification steps had begun, the designer then “…re- assessed all prior sizing decisions” within the context of PVT. Predictably, sequential simulation effort by the de- signer resulted in a poorly-centered design.
To speed up product release, design effort and time should result in well-centered, robust decisions for faster verification through PVT.
Dr. Ramy Iskander of Intento Design explained, “…the N- Viewer displays transistor level performance of the circuit under all possible biasing choices. Our electrical param- eter approach, contrary to size-based exploration, is well bounded. This provides a unique opportunity to view the full, accurate performance range, and to make better trade-off choices and decisions”.
Eliminating design-by-simulation provides a drastic im- provement in product development.
With increased technology complexity, the analog de- signer needs better tools. “…ID-Xplore N-Viewer pre- centering changed designer behaviors and resulted in a better design flow. This gained us time savings at the de- sign phase and gave a “fast-pass” through the verification phase for blocks which had been pre-centered.”