Layout Area Reduction

How do analog designers reduce layout area while still ensuring the yield performance over PVT corners? With design intuition and plenty of extensive SPICE level simulation – that’s how.

Can we at least predict how long it would take to achieve the reduction spec? Is the maximum area reduction that might be achieved ever known? The answer is no and no – with this trial and error method luck plays an important role.

With ID-Xplore, design intuition is accelerated by intelligent exploration algorithms, design space partitioning, and precise transistor sizing for accurate inversion control. All results are quickly and simultaneously viewable for immediate trade-off analysis to select best performance versus block size.

This is industry-first display of SPICE accurate sizing and performance control that allows pre-centering for PVT management and selection of minimum total layout area.

Ramy Iskander clarifies:
“Clearly, the business trade-off with a layout reduction project is the race against optimal design re-sizing, possible softening of performance specifications, and the planned product release date to keep the market placement. Profit margin gained by layout reduction cannot be realized if the scheduled tape-out is not met. For this, ID-Xplore provides an extremely fast SPICE-accurate exploration of all possible combinations of bias and sizing. Each block of the system can be individually assessed for performance and layout savings over PVT.”

Yes, with ID-Xplore you can have your cake and eat it too – achieve the larger area reduction than requested – and in the shorter time. And the trade-off choice and final decision are always in the hands of a designer.

My Intention? Absolute Minimum Layout Area
A rail-to-rail complementary input CMOS operational transconductance amplifier (OTA) had a folded-cascade output stage with variable drive strength to accommodate capacitive load conditions varying from 0.5 pF to 15 pF. The designer wanted to understand the minimum layout area that would satisfy the design requirements for all loads over process, voltage, and temperature (PVT) variation.

Using ID-Xplore, 30 transistors in the OTA were grouped into 12 constraints using 17 unique electrical parameters. The designer explored a range of electrical parameters, resulting in over 22 possible full circuit transistor sizing solutions satisfying performance requirements. From these, the designer selected a well-centered solution with minimal layout. Transistor sizing was updated to the OpenAccess database in a single-click. Analysis for PVT was completed in the standard tool flow. A few (4) failing corners were brought back into ID-Xplore to find sizing solutions to satisfy.

Contact Intento Design today to explore a design services contract or product demo to see how ID-Xplore can help you with achieving your product area specs while surpassing your project timelines.