Meeting performance and linearity requirements in an analog IC means controlling power consumption.
In modern semiconductor processes, controlling the power/energy versus performance trade-off requires operating in the moderate inversion region even for relatively fast circuits. The moderate inversion region is complex, and getting sizing right is difficult.
ID-Xplore precision sizing operations use SPICE accurate techniques to control the transistor parameters and provide designers with data needed to quickly and confidently make the best decision.
For switched-capacitor (SC) analog to digital converters, overall performance vs. power is often limited by the quality of the OTA. Technical difficulties encountered during specific phases of SC feedback can make it unclear if OTA objectives can be met with a different sizing solution or if increased power is required. Ensuring performance is sufficient over the range of switched capacitor loading is crucial and must be obtained within a strict power budget. To avoid product development delay, obtaining a quick and clear answer is important.
The Technical Problem
To ensure converter performance accuracy for this client, sufficient phase margin and a periodic steady state gain gain of 65 dB is required over all phases of the SC common-mode-feedback (CMFB). However, simulations had shown an insufficient gain performance of only 45 dB during one phase of the CMFB. The amplifier had 34 ns allotted slew time and 68 ns linear settling time, and current consumption at the block was specified to be less than 230 μ A. Was it possible to achieve the necessary gain within the power budget?
The Solution – ID-XploreTM Design Exploration
An ID-Xplore exploration was launched to examine all possible sizing variations with different power consumption levels.
ID-Xplore Operations Entering Design Constraints & Exploring
An ID-Xplore Intention view was created using 11 constraints for 40 transistors in the OTA. The 33 global parameters were identified for exploration. A full design-space consisting of over a billion points was intelligently partitioned into < 100 points and results were collected in a single afternoon.
From the exploration, there were 6 valid fully sized schematic solutions proposed. For each uniquely sized solution, the testbench was simulated to obtain precision performance results.
Using ID-Xplore data obtained from extensive transistor sizing and testbench simulation at controlled power levels, the OTA best-case gain vs. power-consumption relationship was extracted in just hours.
Extensive transistor accurate exploration quickly showed that transistor-sizing alone was insufficient to satisfy the specifications. A power trade-off was necessary to ensure amplifier gain in all phases of the CMFB clock.
By the end of the day, the multi-site design team had discussed the results and made the decision to change the OTA power budget.